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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9764* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 14-bit, 125 msps txdac ? d/a converter functional block diagram features member of pin-compatible txdac product family 125 msps update rate 14-bit resolution excellent sfdr and imd differential current outputs: 2 ma to 20 ma power dissipation: 190 mw @ 5 v to 45 mw @ 3 v power-down mode: 25 mw @ 5 v on-chip 1.20 v reference single +5 v or +3 v supply operation packages: 28-lead soic and tssop edge-triggered latches applications communication transmit channel: basestations adsl/hfc modems instrumentation product description the AD9764 is the 14-bit resolution member of the txdac series of high performance, low power cmos digital-to-analog converters (dacs). the txdac family, which consists of pin compatible 8-, 10-, 12-, and 14-bit dacs, is specifically opti- mized for the transmit signal path of communication systems. all of the devices share the same interface options, small outline package and pinout, providing an upward or downward compo- nent selection path based on performance, resolution and cost. the AD9764 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the AD9764s flexible single-supply operating range of 2.7 v to 5.5 v and low power dissipation are well suited for portable and low power applications. its power dissipation can be further reduced to a mere 45 mw with a slight degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 25 mw. the AD9764 is manufactured on an advanced cmos process. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge-triggered input latches and a 1.2 v temperature compensated bandgap refer- ence have been integrated to provide a complete monolithic dac solution. flexible supply options support +3 v and +5 v cmos logic families. the AD9764 is a current-output dac with a nominal full-scale output current of 20 ma and > 100 k w output impedance. txdac is a registered trademark of analog devices, inc. *patent pending. differential current outputs are provided to support single- ended or differential applications. matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. the current outputs may be tied directly to an output resistor to provide two complemen- tary, single-ended voltage outputs or fed directly into a trans- former. the output voltage compliance range is 1.25 v. the on-chip reference and control amplifier are configured for maximum accuracy and flexibility. the AD9764 can be driven by the on-chip reference or by a variety of external reference voltages. the internal control amplifier, which provides a wide (>10:1) adjustment span, allows the AD9764 full-scale current to be adjusted over a 2 ma to 20 ma range while maintaining excellent dynamic performance. thus, the AD9764 may operate at reduced power levels or be adjusted over a 20 db range to provide additional gain ranging capabilities. the AD9764 is available in 28-lead soic and tssop packages. it is specified for operation over the ind ustrial temperature range. product highlights 1. the AD9764 is a member of the txdac product family that provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. manufactured on a cmos process, the AD9764 uses a pro- prietary switching technique that enhances dynamic perfor- mance beyond that previously attainable by higher power/cost bipolar or bicmos devices. 3. on-chip, edge-triggered input cmos latches readily interface to +3 v and +5 v cmos logic families. the AD9764 can support update rates up to 125 msps. 4. a flexible single-supply operating range of 2.7 v to 5.5 v, and a wide full-scale current adjustment span of 2 ma to 20 ma, allows the AD9764 to operate at reduced power levels. 5. the current output(s) of the AD9764 can be easily config- ured for various single-ended or differential circuit topologies. 50pf comp1 +1.20v ref avdd acom reflo comp2 current source array 0.1 m f +5v segmented switches lsb switches refio fs adj dvdd dcom clock +5v r set 0.1 m f clock i outa i outb 0.1 m f latches AD9764 sleep digital data inputs ( db13Cdb0 )
rev. b C2C AD9764Cspecifications dc specifications parameter min typ max units resolution 14 bits dc accuracy 1 integral linearity error (inl) t a = +25 c C4.5 2.5 +4.5 lsb t min to t max C6.5 +6.5 lsb differential nonlinearity (dnl) t a = +25 c C2.5 1.5 +2.5 lsb t min to t max C4.5 +4.5 lsb analog output offset error C0.025 +0.025 % of fsr gain error (without internal reference) C2 1 +2 % of fsr gain error (with internal reference) C7 1 +7 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range C1.0 1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.08 1.20 1.32 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m w small signal bandwidth (w/o c comp1 ) 4 1.4 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 5 2.7 5.0 5.5 v dvdd 2.7 5.0 5.5 v analog supply current (i avdd )2530ma digital supply current (i dvdd ) 6 1.5 4 ma supply current sleep mode (i avdd ) 5.0 8.5 ma power dissipation 6 (5 v, i outfs = 20 ma) 133 170 mw power dissipation 7 (5 v, i outfs = 20 ma) 190 mw power dissipation 7 (3 v, i outfs = 2 ma) 45 mw power supply rejection ratio 8 avdd C0.4 +0.4 % of fsr/v power supply rejection ratio 8 dvdd C0.025 +0.025 % of fsr/v operating range C40 +85 c notes 1 measured at i outa , driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external buffer amplifier to drive any external load. 4 reference bandwidth is a function of external cap at comp1 pin and signal level. 5 for operation below 3 v, it is recommended that the output current be reduced to 12 ma or less to maintain optimum performance. 6 measured at f clock = 25 msps and f out = 1.0 mhz. 7 measured as unbuffered voltage output with i outfs = 20 ma and 50 w r load at i outa and i outb , f clock = 100 msps and f out = 40 mhz. 8 5% power supply variation. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted)
rev. b C3C AD9764 dynamic specifications parameter min typ max units dynamic performance maximum output update rate (f clock ) 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ ? hz output noise (i outfs = 2 ma) 30 pa/ ? hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output t a = +25 c 75 82 dbc t min to t max 73 dbc C6 dbfs output 85 dbc C12 dbfs output 77 dbc C18 dbfs output 70 dbc f clock = 50 msps; f out = 1.00 mhz 80 dbc f clock = 50 msps; f out = 2.51 mhz 77 dbc f clock = 50 msps; f out = 5.02 mhz 70 dbc f clock = 50 msps; f out = 20.2 mhz 58 dbc spurious-free dynamic range within a window f clock = 25 msps; f out = 1.00 mhz; 2 mhz span t a = +25 c 78 89 dbc t min to t max 76 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 84 dbc f clock = 100 msps; f out = 5.04 mhz; 4 mhz span 84 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz t a = +25 c C78 C74 dbc t min to t max C72 dbc f clock = 50 mhz; f out = 2.00 mhz C75 dbc f clock = 100 mhz; f out = 2.00 mhz C75 dbc multitone power ratio (eight tones at 110 khz spacing) f clock = 20 msps; f out = 2.00 mhz to 2.99 mhz 0 dbfs output 73 dbc C6 dbfs output 76 dbc C12 dbfs output 73 dbc C18 dbfs output 64 dbc notes 1 measured single-ended into 50 w load. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, differential tran sformer coupled output, 50 v doubly terminated, unless otherwise noted)
rev. b AD9764 C4C digital specifications parameter min typ max units digital inputs logic 1 voltage @ dvdd = +5 v 3.5 5 v logic 1 voltage @ dvdd = +3 v 2.1 3 v logic 0 voltage @ dvdd = +5 v 0 1.3 v logic 0 voltage @ dvdd = +3 v 0 0.9 v logic 1 current C10 +10 m a logic 0 current C10 +10 m a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw ) 3.5 ns specifications subject to change without notice. 0.1% 0.1% t s t h t lpw t pd t st db0Cdb13 clock iouta or ioutb figure 1. timing diagram ordering guide temperature package package model range description options* AD9764ar C40 c to +85 c 28-lead 300 mil soic r-28 AD9764aru C40 c to +85 c 28-lead tssop ru-28 AD9764-eb evaluation board *r = small outline ic, ru = tssop. thermal characteristics thermal resistance 28-lead 300 mil soic q ja = 71.4 c/w q jc = 23 c/w 28-lead tssop q ja = 97.9 c/w q jc = 14.0 c/w absolute maximum ratings* with parameter respect to min max units avdd acom C0.3 +6.5 v dvdd dcom C0.3 +6.5 v acom dcom C0.3 +0.3 v avdd dvdd C6.5 +6.5 v clock, sleep dcom C0.3 dvdd + 0.3 v digital inputs dcom C0.3 dvdd + 0.3 v i outa , i outb acom C1.0 avdd + 0.3 v comp1, comp2 acom C0.3 avdd + 0.3 v refio, fsadj acom C0.3 avdd + 0.3 v reflo acom C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9764 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b AD9764 C5C pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 AD9764 nc = no connect (msb) db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 i outa i outb acom comp1 fs adj refio reflo sleep pin function descriptions pin no. name description 1 db13 most significant data bit (msb). 2C13 db12Cdb1 data bits 1C12. 14 db0 least significant data bit (lsb). 15 sleep power-down control input. active high. c ontains active pull-down circuit; it may be left u nterminated if not used. 16 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 m f capacitor to acom when internal reference activated. 18 fs adj full-scale current output adjust. 19 comp1 bandwidth/noise reduction node. add 0.1 m f to avdd for optimum performance. 20 acom analog common. 21 i outb complementary dac current output. full-scale current when all data bits are 0s. 22 i outa dac current output. full-scale current when all data bits are 1s. 23 comp2 internal bias node for switch driver circuitry. decouple to acom with 0.1 m f capacitor. 24 avdd analog supply voltage (+2.7 v to +5.5 v). 25 nc no internal connection. 26 dcom digital common. 27 dvdd digital supply voltage (+2.7 v to +5.5 v). 28 clock clock input. data latched on positive edge of clock.
rev. b AD9764 C6C definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is reported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are varied over a specified range. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the sum of the rms value of the first six harmonic com ponents to the rms value of the measured output signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range for an output containing mul- tiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. 50pf comp1 +1.20v ref avdd acom reflo comp2 pmos current source array 0.1 m f segmented switches for db13Cdb5 lsb switches refio fs adj dvdd dcom clock +5v r set 2k v 0.1 m f dvdd dcom i outa i outb 0.1 m f AD9764 sleep 50 v retimed clock output* latches digital data tektronix awg-2021 lecroy 9210 pulse generator clock output 50 v 20pf 50 v 20pf 100 v to hp3589a spectrum/ network analyzer 50 v input mini-circuits t1-1t * awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. +5v figure 2. basic ac characterization test setup
rev. b AD9764 C7C typical ac characterization curves (avdd = +5 v, dvdd = +3 v, i outfs = 20 ma, 50 v doubly terminated load, differential output, t a = +25 8 c, sfdr up to nyquist, u nless otherwise noted) frequency C mhz sfdr C dbc 90 85 40 0.1 1 100 10 55 45 50 65 60 80 70 75 5 msps 25 msps 50 msps 100 msps figure 3. sfdr vs. f out @ 0 dbfs frequency C mhz sfdr C dbc 90 85 40 05 25 10 15 20 60 55 50 45 80 70 75 65 0dbfs C6dbfs C12dbfs figure 6. sfdr vs. f out @ 50 msps a out C dbfs sfdr C dbc 90 80 50 C30 C25 0 C20 C15 C10 C5 70 60 455khz @ 5 msps 2.27mhz @ 25 msps 4.55mhz @ 50 msps 9.09mhz @ 100 msps figure 9. single-tone sfdr vs. a out @ f out = f clock /11 frequency C mhz sfdr C dbc 90 85 40 0 0.5 2.5 1.0 1.5 2.0 60 55 50 45 80 70 75 65 0dbfs C6dbfs C12dbfs figure 4. sfdr vs. f out @ 5 msps frequency C mhz sfdr C dbc 90 85 40 010 50 20 30 40 60 55 50 45 80 70 75 65 0dbfs C6dbfs C12dbfs figure 7. sfdr vs. f out @100 msps a out C dbfs sfdr C dbc 90 80 50 C30 C25 0 C20 C15 C10 C5 70 60 1mhz @ 5 msps 5mhz @ 25 msps 10mhz @ 50 msps 20mhz @ 100 msps figure 10. single-tone sfdr vs. a out @ f out = f clock /5 frequency C mhz sfdr C dbc 90 40 02 12 46810 85 60 55 50 45 80 75 65 70 0dbfs C6dbfs C12dbfs figure 5. sfdr vs. f out @ 25 msps frequency C mhz 90 85 50 0.0 2.0 10.0 4.0 6.0 8.0 70 65 60 55 80 75 5ma @ 3v 5ma @ 5v 10ma @ 3v 10ma @ 5v 20ma @ 3v 20ma @ 5v sfdr C dbc figure 8. sfdr vs. f out and i outfs @ 25 msps and 0 dbfs a out C dbfs sfdr C dbc 90 80 50 C30 C25 0 C20 C15 C10 C5 70 60 0.675/0.725mhz @ 5 msps 3.38/3.63mhz @ 25 msps 13.5/14.5mhz @ 100 msps 6.75/7.25 @ 50 msps figure 11. dual-tone sfdr vs. a out @ f out = f clock /7
rev. b AD9764 C8C dbc C70 C75 C95 000.0e+0 40.0e+6 80.0e+6 120.0e+6 C80 C85 C90 2nd harmonic 3rd harmonic 4th harmonic figure 12. thd vs. f clock @ f out = 2 mhz code error C lsb 2.0 C2.0 0 16000 4000 8000 12000 1.5 0.0 C0.5 C1.0 C1.5 1.0 0.5 figure 15. typical inl 000.0e+0 7.5e+6 15.0e+6 22.5e+6 10db C div 0 C10 C90 C50 C60 C70 C80 C20 C40 C30 f clk = 50msps f out = 1.25mhz sfdr = 78dbc amplitude = 0dbfs figure 18. single-tone sfdr f clock C msps snr C db 85 80 60 0 10 100 20 30 40 50 60 70 80 90 75 70 65 i outfs = 5ma, dvdd = +5v i outfs = 5ma, dvdd = +3v i outfs = 10ma, dvdd = +5v i outfs = 10ma, dvdd = +3v i outfs = 20ma, dvdd = +5v i outfs = 20ma, dvdd = +3v figure 13. snr vs. f clock @ f out = 2.0 mhz code error C lsb 2.0 C1.0 0 16000 4000 8000 12000 1.5 1.0 0.5 0.0 C0.5 figure 16. typical dnl 0e+0 25e+6 5e+6 10e+6 15e+6 20e+6 10db C div 0 C10 C90 C50 C60 C70 C80 C20 C40 C30 f clk = 50msps f out1 = 6.75mhz f out2 = 7.25mhz sfdr = 69dbc amplitude = 0dbfs figure 19. dual-tone sfdr output frequency C mhz sfdr C dbc 80 70 50 1 10 100 60 i diff @ 0dbfs i diff @ C6dbfs i a @ 0dbfs i a @ C6dbfs figure 14. differential vs. single- ended sfdr vs. f out @ 50 msps temperature C 8 c sfdr C dbc 80 75 50 C40 C20 80 60 70 65 60 55 40 20 0 2.5mhz 10mhz 40mhz figure 17. sfdr vs. temperature @ 100 msps, 0 dbfs 10db C div 0 C70 C100 C10 C60 C80 C90 C40 C50 C20 C30 000.0e+0 7.5e+6 15.0e+6 22.5e+6 f clk = 50msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 66dbc amplitude = 0dbfs figure 20. four-tone sfdr
rev. b AD9764 C9C functional description figure 21 shows a simplified block diagram of the AD9764. the AD9764 consists of a large pmos current source array that is capable of providing up to 20 ma of total current. the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted frac- tions of the middle bits current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (i.e., >100 k w ). all of these current sources are switched to one or the other of the two output nodes (i.e., i outa or i outb ) via pmos differen- tial current switches. the switches are based on a new architec- ture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the dif- ferential current switches. the analog and digital sections of the AD9764 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 volt to 5.5 volt range. the digital section, which is capable of operating up to a 125 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v bandgap voltage reference and a reference control amplifier. the full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 ma to 20 ma via an exter- nal resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is mirrored over to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times the value of i ref . dac transfer function the AD9764 provides complementary current outputs, i outa and i outb . i outa will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 16383) while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as: i outa = ( dac code /16384) i outfs (1) i outb = (16383 C dac code )/16384 i outfs (2) where dac code = 0 to 16383 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the i outa and i outb nodes is simply: v outa = i outa r load (5) v outb = i outb r load (6) note that the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain speci- fied distortion and linearity performance. the differential voltage, v diff , appearing across i outa and i outb is: v diff = ( i outa C i outb ) r load (7) substituting the values of i outa , i outb and i ref ; v diff can be expressed as: v diff = {(2 dac code C 16383)/16384} v diff = { (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the AD9764 differentially. first, the differential op- eration will help cancel common-mode error sources associated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the AD9764 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relation- ship as shown in equation 8. digital data inputs ( db13Cdb0 ) 50pf comp1 +1.20v ref avdd acom reflo comp2 pmos current source array 0.1 m f +5v segmented switches for db13Cdb5 lsb switches refio fs adj dvdd dcom clock +5v r set 2k v 0.1 m f i outa i outb 0.1 m f AD9764 sleep i ref v refio clock i outb i outa r load 50 v v outb v outa r load 50 v v diff = v outa C v outb latches figure 21. functional block diagram
rev. b AD9764 C10C reference operation the AD9764 contains an internal 1.20 v bandgap reference that can be easily disabled and overridden by an external reference. refio serves as either an input or output, depending on whether the internal or external reference is selected. if reflo is tied to acom, as shown in figure 22, the internal reference is activated, and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 m f or greater from refio to reflo. also, refio should be buffered with an external amplifier having an input bias current less than 100 na if any additional loading is required. 50pf comp1 +1.2v ref avdd reflo current source array 0.1 m f +5v refio fs adj 2k v 0.1 m f AD9764 additional load optional external ref buffer figure 22. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 23. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 m f compensation capacitor is not required since the internal reference is disabled, and the high input im- pedance (i.e., 1 m w ) of refio minimizes any loading of the external reference. 50pf comp1 +1.2v ref avdd reflo current source array 0.1 m f avdd refio fs adj r set AD9764 external ref i ref = v refio /r set avdd reference control amplifier v refio figure 23. external reference configuration reference control amplifier the AD9764 also contains an internal control amplifier that is used to regulate the dacs full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 23, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied over to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting iref between 62.5 m a and 625 m a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the AD9764, which is pro- portional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 1.4 mhz and can be reduced by connecting an external capacitor between comp1 and avdd. the output of the control amplifier, comp1, is internally compensated via a 50 pf capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference ampli- fier. figure 24 shows the relationship between the external capacitor and the small signal C3 db bandwidth of the refer- ence amplifier. since the C3 db bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input response can be approximated. comp1 capacitor C nf 1000 10 0.1 0.1 1000 1 bandwidth C khz 10 100 figure 24. external comp1 capacitor vs. C3 db bandwidth the optimum distortion performance for any reconstructed waveform is obtained with a 0.1 m f external capacitor installed. thus, if i ref is fixed for an application, a 0.1 m f ceramic chip capacitor is recommended. also, since the control amplifier is optimized for low power operation, multiplying applications requiring large signal swings should consider using an external control amplifier to enhance the applications overall large signal multiplying bandwidth and/or distortion performance. there are two methods in which i ref can be varied for a fixed r set . the first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of refio is varied over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifier or dac, thus allowing i ref to be varied for a fixed r set . since the input impedance of refio is approximately 1 m w , a simple, low cost r-2r ladder dac configured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 25 using the ad7524 and an external 1.2 v reference, the ad1580.
rev. b AD9764 C11C the second method may be used in a dual-supply system in which the common-mode voltage of refio is fixed, and i ref is varied by an external voltage, v gc , applied to r set via an ampli- fier. an example of this method is shown in figure 26 in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 v. the external voltage, v gc , is referenced to acom and should not exceed 1.2 v. the value of r set is such that i refmax and i refmin do not exceed 62.5 m a and 625 m a, respectively. the associated equations in figure 26 can be used to determine the value of r set . 50pf comp1 avdd reflo current source array avdd refio fs adj r set AD9764 i ref optional bandlimiting capacitor v gc 1 m f i ref = (1.2Cv gc )/r set with v gc < v refio and 62.5 m a # i ref # 625a +1.2v ref figure 26. dual-supply gain control circuit in some applications, the user may elect to use an external control amplifier to enhance the multiplying bandwidth, distortion performance and/or settling time. external amplifiers capable of driving a 50 pf load such as the ad817 are suitable for this purpose. it is configured in such a way that it is in parallel with the weaker internal reference amplifier as shown in figure 27. in this case, the external amplifier simply overdrives the weaker reference control amplifier. also, since the internal control amplifier has a limited current output, it will sustain no damage if overdriven. 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set AD9764 v ref input external control amplifier figure 27. configuring an external reference control amplifier analog outputs the AD9764 produces two complementary current outputs, i outa and i outb , which may be configured for single-end or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. figure 28 shows the equivalent analog output circuit of the AD9764 consisting of a parallel combination of pmos differen- tial current switches associated with each segmented current source. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos s witches and is typically 100 k w in parallel with 5 pf. due to the na- ture of a pmos device, the output impedance is also slightly depe ndent on the output voltage (i.e., v outa and v outb ) and, to a lesser extent, the analog supply voltage, avdd, and full-scale current, i outfs . although the output impedances signal depen- dency can be a source of dc nonlinearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted. AD9764 avdd i outa i outb r load r load figure 28. equivalent analog output circuit i outa and i outb also have a negative and positive voltage compli- ance range. the negative output compliance range of C1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break down of the output stage and affect the r eliability of the AD9764. the posi- tive output compliance range is slightly dependent on the full- scale output current, i outfs . it degrades slightly from its nominal 1.2v 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set AD9764 i ref = v ref /r set avdd optional bandlimiting capacitor v ref v dd r fb out1 out2 agnd db7Cdb0 ad7524 ad1580 0.1v to 1.2v figure 25. single-supply gain control circuit
rev. b AD9764 C12C 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. operation beyond the positive compli ance range will induce clipping of the output signal which severely degrades the AD9764s linearity and distortion performance. for applications requiring the optimum dc linearity, i outa and/ or i outb should be maintained at a virtual ground via an i-v op amp configuration. maintaining i outa and/or i outb at a virtual ground keeps the output impedance of the AD9764 fixed, signifi- cantly reducing its effect on linearity. however, it does not necessarily lead to the optimum distortion performance due to limitations of the i-v op amp. note that the inl/dnl speci- fications for the AD9764 are measured in this manner using i outa . in addition, these dc linearity specifica tions remain virtually unaffected over the specified power supply range of 2.7 v to 5.5 v. operating the AD9764 with reduced voltage output swings at i outa and i outb in a differential or single-ended output configu- ration reduces the signal dependency of its output impedance thus enhancing distortion performance. although the voltage compliance range of i outa and i outb extends from C1.0 v to +1.25 v, optimum distortion performance is achieved when the maximum full-scale signal at i outa and i outb does not exceed approximately 0.5 v. a properly selected transformer with a grounded center-tap will allow the AD9764 to provide the re- quired power and voltage levels to different loads while main- taining reduced voltage swings at i outa and i outb . dc-coupled applications requiring a differential or single-ended output con- figuration should size r load accordingly. refer to applying the AD9764 section for examples of various output configurations. the most significant improvement in the AD9764s distortion and noise performance is realized using a differential output configuration. the common-mode error sources of both i outa and i outb can be substantially reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the recons tructed waveforms frequency content increases and/or its amplitude decreases. this is evident in figure 14, which com pares the differential vs. single-ended pe rformance of the ad 9764 at 50 msps for 0.0 and C6.0 dbfs single tone waveforms over frequency. the distortion and noise performance of the AD9764 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, i outfs . operating the analog supply at 5.0 v ensures maximum headroom for its internal pmos current sources and differential switches leading to improved distortion performance as shown in figure 8. al though i outfs can be set between 2 ma and 20 ma, selecting an i outfs of 20 ma will provide the best distortion and noise performance also shown in figure 8. the noise performance of the AD9764 is affected by the digital supply (dvdd), output frequency, and increases with increasing clock rate as shown in figure 13. operating the AD9764 with low voltage logic levels between 3 v and 3.3 v will slightly reduce the amount of on-chip digital noise. in summary, the AD9764 achieves the optimum distortion and noise performance under the following conditions: (1) differential operation. (2) positive voltage swing at i outa and i outb limited to +0.5 v. (3) i outfs set to 20 ma. (4) analog supply (avdd) set at 5.0 v. (5) digital supply (dvdd) set at 3.0 v to 3.3 v with appro- priate logic levels. note that the ac performance of the AD9764 is characterized under the above mentioned operating conditions. digital inputs the AD9764s digital input consists of 14 data input pins and a clock input pin. the 14-bit parallel data inputs follow standard positive binary coding where db13 is the most significant bit (msb), and db0 is the least significant bit (lsb). i outa pro- duces a full-scale output current when all data bits are at logic 1. i outb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. the dac output is updated following the rising edge of the clock as shown in figure 1 and is designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulse- width. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. the digital inputs are cmos-compatible with logic thresholds, v threshold, set to approximately half the digital positive supply (dvdd) or v threshold = dvdd /2 ( 20%) the internal digital circuitry of the AD9764 is capable of oper ating over a digital supply range of 2.7 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh(max) . a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. figure 29 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the AD9764 remains enabled if this input is left disconnected. dvdd digital input figure 29. equivalent digital input
rev. b AD9764 C13C since the AD9764 is capable of being updated up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. operating the AD9764 with reduced logic swings and a corresponding digital supply (dvdd) will result in the lowest data feedthrough and on-chip digital noise. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9764 as well as its required min/max input logic level thresholds. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 w to 100 w ) between the ad 9764 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain clean digital inputs. the external clock driver circuitry should provide the AD9764 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. note, that the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., dvdd/2) and meets the min/max logic threshold. this will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effec- tive clock duty cycle and, subsequently, cut into the required data setup and hold times. sleep mode operation the AD9764 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 2.7 v to 5.5 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. this digital input also con- tains an active pull-down circuit that ensures the AD9764 re- mains enabled if this input is left disconnected. the sleep input with active pull-down requires <40 m a of drive current. the power-up and power-down characteristics of the AD9764 are dependent upon the value of the compensation capacitor connected to comp1. with a nominal value of 0.1 m f, the AD9764 takes less than 5 m s to power down and approximately 3.25 ms to power back up. note, the sleep mode should not be used when the external control amplifier is used as shown in figure 27. power dissipation the power dissipation, p d , of the AD9764 is dependent on several factors, including: (1) avdd and dvdd, the power supply voltages; (2) i outfs , the full-scale current output; (3) f clock , the update rate; and (4) the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs, as shown in figure 30, and is insensitive to f clock . i outfs C ma 30 0 220 4 6 8 10 12141618 25 20 15 10 5 i avdd C ma figure 30. i avdd vs. i outfs conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 31 and 32 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note, how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. ratio C f out /f clk 18 16 0 0.01 1 0.1 i dvdd C ma 8 6 4 2 12 10 14 5msps 25msps 50msps 100msps 125msps figure 31. i dvdd vs. ratio @ dvdd = 5 v ratio C f out /f clk 8 0 0.01 1 0.1 i dvdd C ma 6 4 2 5msps 25msps 50msps 100msps 125msps figure 32. i dvdd vs. ratio @ dvdd = 3 v
rev. b AD9764 C14C applying the AD9764 output configurations the following sections illustrate some typical output configura- tions for the AD9764. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropriately sized load resistor, r load , referred to acom. this configura- tion may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus convert- ing i outa or i outb into a negative unipolar voltage. this con- figuration provides the best dc linearity since i outa or i outb is maintained at a virtual ground. note, i outa provides slightly better performance than i outb . differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 33. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers passband. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of com- mon-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load AD9764 22 21 mini-circuits t1-1t optional r diff i outa i outb figure 33. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appear- ing at i outa and i outb (i.e., v outa and v outb ) swing sym- metrically around acom and should be maintained with the specified output compliance range of the AD9764. a differential resistor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approxi- mately half the signal power will be dissipated across r diff . differential using an op amp an op amp can also be used to perform a differential-to-single- ended conversion as shown in figure 34. the AD9764 is con- figured with two equal load resistors, r load , of 25 w . the differential voltage developed across i outa and i outb is con- verted to a single-ended signal via the differential op amp con- figuration. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion perfor- mance by preventing the dacs high slewing output from over- loading the op amps input. AD9764 22 i outa i outb 21 c opt 500 v 225 v 225 v 500 v 25 v 25 v ad8047 figure 34. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential perform- ance of the AD9764 while meeting other system level objectives (i.e., cost, power) should be selected. the op amps differential gain, its gain setting resistor values and full-scale output swing capabilities should all be considered when optimizing this circuit. the differential circuit shown in figure 35 provides the neces- sary level-shifting required in a single supply system. in this case, avdd, which is the positive analog supply for both the AD9764 and the op amp, is also used to level-shift the differ- ential output of the AD9764 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. AD9764 22 i outa i outb 21 c opt 500 v 225 v 225 v 1k v 25 v 25 v ad8041 1k v avdd figure 35. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 36 shows the AD9764 configured to provide a unipolar output range of approximately 0 v to +0.5 v for a doubly termi- nated 50 w cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 w . in this case, r load represents the equivalent load resistance seen by i outa or i outb . the unused output (i outa or i outb ) can be connected to acom directly or via a matching r load . different values of
rev. b AD9764 C15C i outfs and r load can be selected as long as the positive compli- ance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl) as discussed in the ana- log output section of this data sheet. for optimum inl perfor- mance, the single-ended, buffered voltage output configuration is suggested. AD9764 i outa i outb 21 50 v 25 v 50 v v outa = 0 to +0.5v i outfs = 20ma 22 figure 36. 0 v to +0.5 v unbuffered voltage output single-ended buffered voltage output configuration figure 37 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the AD9764 output current. u1 maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output impedance effect on the dacs inl performance as discussed in the ana- log output section. although this single-ended configuration typically provides the best dc linearity performance, its ac distor- tion performance at higher dac update rates may be limited by u1s slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the prod uct of r fb and i outfs . the full-scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. AD9764 22 i outa i outb 21 c opt 200 v u1 v out = i outfs 3 r fb i outfs = 10ma r fb 200 v figure 37. unipolar buffered voltage output power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection, placement and routing and supply bypassing and grounding. figures 42C47 illustrate the recommended printed circuit board ground, power and signal plane layouts that are implemented on the AD9764 evaluation board. proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the AD9764 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physi- cally possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close as physically as possible. for those applications requiring a single +5 v or +3 v supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in figure 38. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tantalum capacitors. 100 m f elect. 10-22 m f tant. 0.1 m f cer. ttl/cmos logic circuits +5v or +3v power supply ferrite beads avdd acom figure 38. differential lc filter for single +5 v or +3 v applications maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9764. if properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding current trans- port, etc. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous volt- age drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the pack- age as possible in order to minimize the sharing of conduction paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed discussion of the implementation and con- struction of high speed, mixed signal printed circuit boards, refer to analog devices application notes an-280 and an-333.
rev. b AD9764 C16C multitone performance considerations and characterization the frequency domain performance of high speed dacs has traditionally been characterized by analyzing the spectral output of a reconstructed full-scale (i.e., 0 dbfs), single-tone sine wave at a particular output frequency and update rate. although this characterization data is useful, it is often insufficient to reflect a dacs performance for a reconstructed multitone or spread- spectrum waveform. in fact, evaluating a dacs spectral performance using a f ull-scale, single tone at the highest specified frequency (i.e., f h ) of a bandlimited waveform is typically indicative of a dacs worst-case performance for that given waveform. in the time domain, this full-scale sine wave repre- sents the lowest peak-to-rms ratio or crest factor (i .e., v peak /v rms) that this bandlimited signal will encounter. magnitude C dbm frequency C mhz C10 C70 C110 2.19 2.81 2.25 2.31 2.38 2.44 2.50 2.56 2.63 2.69 2.75 C20 C60 C80 C100 C40 C50 C90 C30 figure 39a. multitone spectral plot time 1.0000 0.8000 C1.0000 volts C0.2000 C0.4000 C0.6000 C0.8000 0.2000 0.0000 0.4000 0.6000 figure 39b. time domain snapshot of the multitone waveform however, the inherent nature of a multitone, spread spectrum, or qam waveform, in which the spectral energy of the wave- form is spread over a designated bandwidth, will result in a higher peak-to-rms ratio when compared to the case of a simple sine wave. as the reconstructed waveforms peak-to-average ratio increases, an increasing amount of the signal energy is concentrated around the dacs midscale value. figure 39a is just one example of a bandlimited multitone vector (i.e., eight tones) ce ntered around one-half the nyquist bandwidth (i.e., f clock /4). t his particular multitone vector, has a peak-to-rms ratio of 13.5 db com pared to a sine waves peak-to-rms ratio of 3 db. a snapshot of this reconstructed multitone vector in the time domain as shown in figure 39b reveals the higher signal content around the midscale value. as a result, a dacs small-scale dynamic and static linearity becomes increas- ingly critical in obtaining low intermodulation distortion and maintaining sufficient carrier-to-noise ratios for a given modula- tion scheme. a dacs small-scale linearity performance is also an important consideration in applications where additive dynamic range is required for gain control purposes or predistortion signal conditioning. for instance, a dac with sufficient dynamic range can be used to provide additional gain control of its reconstructed signal. in fact, the gain can be controlled in 6 db increments by simply performing a shift left or right on the dacs digital input word. other applications may intentionally predistort a dacs digital input signal to compensate for nonlinearities associated with the s ubsequent analog compo- nents in the signal chain. for example, the signal compression associated with a power amplifier can be compensated for by predisto rting the dacs digital input with the inverse nonlinear transfer function of the power amplifier. in either case, the dacs performance at reduced signal levels should be carefully evaluated. a full-scale single tone will induce all of the dynamic and static nonlinearities present in a dac that contribute to its distortion and hence sfdr performance. referring to figure 3, as the frequency of this reconstructed full-scale, single-tone waveform increases, the dynamic nonlinearities of any dac (i.e., AD9764) tend to dominate thus contributing to the rolloff in its sfdr performance. however, unlike most dacs, which employ an r-2r ladder for the lower bit current segmentation, the AD9764 (as well as other txdac members) exhibits an improvement in distortion performance as the amplitude of a single tone is re- duced from its full-scale level. this improvement in distortion performance at reduced signal levels is evident if one compares the sfdr performance vs. frequency at different amplitudes (i.e., 0 dbfs, C6 dbfs and C12 dbfs) and sample rates as shown in figures 4 through 7. maintaining decent small-scale linearity across the full span of a dac transfer function is also critical in maintaining excellent multitone performance. although characterizing a dacs multitone performance tends to be application-specific, much insight into the potential per- formance of a dac can also be gained by evaluating the dacs swept power (i.e., amplitude) performance for single, dual and multitone test vectors at different clock rates and carrier frequen- cies. the dac is evaluated at different clock rates when recon- structing a specific waveform whose amplitude is decreased in 3 db increments from full-scale (i.e., 0 dbfs). for each specific waveform, a graph showing the sfdr (over nyquist) perfor- mance vs. amplitude can be generated at the different tested clock rates as shown in figures 9C11. note that the carrier(s)- to-clock ratio remains constant in each figure. in each case, an improvement in sfdr performance is seen as the amplitude is reduced from 0 dbfs to approximately C9.0 dbfs. a multitone test vector may consist of several equal amplitude, spaced carriers each representative of a channel within a defined bandwidth as shown in figure 39a. in many cases, one or more tones are removed so the intermodulation distortion performance
rev. b AD9764 C17C of the dac can be evaluated. nonlinearities associated with the dac will create spurious tones of which some may fall back into the empty channel thus limiting a channels carrier-to-noise ratio. other spurious components falling outside the band of interest may also be important, depending on the systems spectral mask and filtering requirements. this particular test vector was centered around one-half the nyquist bandwidth (i.e., f clock /4) with a passband of f clock /16. centering the tones at a much lower region (i.e., f clock /10) would lead to an improvement in performance while centering the tones at a higher region (i.e., f clock /2.5) would result in a degradation in performance. figure 40a shows the sfdr vs. amplitude at different sample rates up to the nyquist frequency while figure 40b shows the sfdr vs. amplitude within the passband of the test vector. in assessing a dacs multitone performance, it is also recommended that several units be tested under exactly the same conditions to determine any performance variability. a out C dbfs sfdr C dbc 80 50 C20 C15 0 C10 C5 70 60 10 msps 100 msps 20 msps 50 msps 40 30 75 65 55 45 35 figure 40a. multitone sfdr vs. a out (up to nyquist) sfdr C dbc 50 70 60 40 75 65 55 45 80 10 msps 20 msps 50 msps 100 msps a out C dbfs C20 C15 0 C10 C5 figure 40b. multitone sfdr vs. a out (within multitone passband) AD9764 evaluation board general description the AD9764-eb is an evaluation board for the AD9764 14-bit dac converter. careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and effectively evaluate the AD9764 in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the AD9764 in various configurations. possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. the digital inputs are designed to be driven directly from various word generators with the onboard option to add a resistor network for proper load termi- nation. provisions are also made to operate the AD9764 with either the internal or external reference or to exercise the power- down feature. refer to the application note an-420, using the ad9760/AD9764/ AD9764-eb evaluation board for a thorough description and operating instructions for the AD9764 evaluation board.
rev. b AD9764 C18C 1098765432 1 r4 10 9 8 7 6 5 4 3 2 1 r7 dvdd 10 9 8 7 6 5 4 3 2 1 r3 1098765432 1 dvdd r6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 10 9 8 7 6 5 4 3 2 1 r5 dvdd 10 9 8 7 6 5 4 3 2 1 r1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c19 c1 c2 c25 c26 c27 c28 c29 16 pindip res pk 16 15 14 13 12 11 10 1 2 3 4 5 6 7 c30 c31 c32 c33 c34 c35 c36 16 pindip res pk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 iouta ioutb acom comp1 fs adj refio reflo sleep u1 AD9764 avdd ct1 a 1 a r15 49.9 v clk jp1 ab 3 2 1 j1 tp1 extclk c7 1 m f c8 0.1 m f avdd a c9 0.1 m f tp8 2 avdd tp11 c11 0.1 m f tp10 tp9 r16 2k v tp14 jp4 c10 0.1 m f out 1 out 2 tp13 r17 49.9 v pdin j2 a a a avdd 3 jp2 tp12 tp7 a c6 10 m f avcc b6 tp6 a c5 10 m f avee b5 tp19 a agnd b4 tp18 tp5 c4 10 m f tp4 avdd b3 tp2 dgnd b2 c3 10 m f tp3 dvdd b1 r20 49.9 v j3 c12 22pf a a r14 0 a 4 5 6 1 3 t1 j7 r38 49.9 v j4 a a jp6a jp6b a r13 open c13 22pf c20 0 r12 open a b a jp7b b a jp7a r10 1k v b a jp8 r9 1k v a b a r35 1k v jp9 r18 1k v a 3 7 6 2 4 ad8047 c21 0.1 m f a c22 1 m f r36 1k v c23 0.1 m f a c24 1 m f avee avcc r37 49.9 v j6 a 3 7 6 2 4 1 2 3 jp5 c15 0.1 m f a avee r46 1k v c17 0.1 m f a 1 2 3 jp3 a b avcc a cw r43 5k v r45 1k v c14 1 m f a r44 50 v extrefin j5 a r42 1k v c16 1 m f a avcc c18 0.1 m f u7 6 2 4 a vin vout gnd ref43 98765432 1 r2 10 a 1098765432 1 dvdd r8 u6 a ad8047 out2 out1 u4 figure 41. evaluation board schematic
rev. b AD9764 C19C figure 42. silkscreen layertop figure 43. component side pcb layout (layer 1)
rev. b AD9764 C20C figure 44. ground plane pcb layout (layer 2) figure 45. power plane pcb layout (layer 3)
rev. b AD9764 C21C figure 46. solder side pcb layout (layer 4) figure 47. silkscreen layerbottom
rev. b AD9764 C22C outline dimensions dimensions shown in inches and (mm). 28-lead, 300 mil soic (r-28) 0.0125 (0.32) 0.0091 (0.23) 8 8 0 8 0.0291 (0.74) 0.0098 (0.25) 3 45 8 0.0500 (1.27) 0.0157 (0.40) 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 28-lead tssop (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 8 0 8 c2467bC1C10/99 printed in u.s.a.

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